1. Field of the Invention
The present invention relates to a semiconductor manufacturing process and in particular to a method of fabricating a dielectric layer suppressing electrostatic charge buildup.
2. Description of the Related Art
Semiconductor technology employs dielectric layers for electrical isolation and separation of conductive layers interconnecting circuits within microelectronic fabrication. When multiple levels of conductor layers are required to interconnect the high density of devices currently being fabricated within a semiconductor device, their separation is accomplished by inter-level metal dielectric (IMD) layers. Silicon oxide-containing dielectric materials may be formed into inter-level metal dielectric (IMD) layers useful in semiconductor technology by chemical vapor deposition (CVD). Many ways of forming a dielectric layer with good properties for certain purposes are widely sought.
For example, Lee, in U.S. Pat. No. 5,605,859, discloses a method for forming a dielectric layer over a polysilicon resistor layer on a glasseous dielectric layer while employing plasma enhanced chemical vapor deposition (PECVD) from silane to form a silicon oxide dielectric layer. The silicon oxide layer is deposited partly over the glasseous layer.
Further, Jang et al., in U.S. Pat. No. 5,741,740, disclose a method for forming a dielectric layer for shallow trench isolation (STI) wherein a conformal silicon oxide layer is first formed in the trench employing silane in a PECVD process, and then a gap filling silicon oxide is formed over the trench and conformal first silicon oxide layer employing SACVD in O3-TEOS.
Still further, Fry, in U.S. Pat. No. 5,786,278, discloses a method for changing the tensile stress in a dielectric layer formed employing O.sub.3-TEOS in a SACVD process with compressive stress. The method employs exposure of the silicon oxide dielectric layer to pressures above atmospheric pressure at temperatures below the stress conversion temperature for the dielectric layer at atmospheric pressure to bring about the conversion of stress.
As the number of devices that may be included on a single semiconductor chip increases, the size of the device is reduced, as is the thickness of the photoresist layer. As well, the aspect of the gap between metal layers increases. In particular, silicon oxide dielectric layers formed by high density plasma chemical vapor deposition (HDPCVD) methods are well suited for these purposes because of the strong physical and electrical properties thereof. High density plasma chemical vapor deposition provides ion-bombardment for etching the sidewalls of the gaps during deposition, such that the deposited dielectric film forms quicker vertically. Thus, the gap-filling properties of the silicon oxide dielectric layer deposited by high density plasma chemical vapor deposition (HDPCVD), as used for IMD, are optimal.
Shufflebotham et al., in U.S. Pat. No. 6,531,377, disclose a method of high density plasma CVD gap-filling. The method comprises depositing a film of SiO2 in gaps with widths less than 0.5 μm and aspect ratios exceeding 1.5:1 on a substrate, generating plasma in a process chamber by energizing gas containing silicon, oxygen and a heavy noble gas such as xenon or krypton.
Moreover, Knorr et al., in U.S. Pat. No. 6,531,377, disclose a method for high aspect ratio gap fill using sequential HDPCVD. In the HDPCVD process, a anisotropic dielectric layers are deposited as required for the particular aspect ratio of the trench, in order to fill the trench completely without voids within the trench dielectric material. However, metal extrusion issue may be produced in the dielectric layers deposited by high density plasma chemical vapor deposition (HDPCVD).
As shown in FIG. 1, a patterned metal layer 102 is formed on the substrate 100. Next, a liner dielectric layer 106 is comformally formed on the mater layer 102 and the substrate 100. Next, a dielectric layer 108 is deposited on the liner dielectric layer 106 to fill gaps between the patterned metal layer 102 and the substrate 100. Due to residual bombardment ions and interrupted bonds in the dielectric layer 108 a number of charges, however, a number of charges, such as fixed charges, defect charges, or dangling bonds, are produced in the dielectric layer 108 deposited by high density plasma chemical vapor deposition (HDPCVD). In order to remove particles from the surface of the dielectric layer 108, water scrubbing S100 using jet scrubber equipment to jet distilled water incident at about 3˜6° is proposed. A large number of electrostatic charges induced by the friction between water and the HDPCVD dielectric layer 108 are, however, excessive, resulting in metal extruding from underlying metal layers to the dielectric layer, observable by scanning electron microscope (SEM). The electrostatic charges promote metal extrusion 106a from the metal layer 102 to the dielectric layer 108. The larger the electrostatic charge, the more serious the metal extrusion.